255 lines
8.6 KiB
HolyC
255 lines
8.6 KiB
HolyC
class @vmsvga_info
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{
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U16 io_base;
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U32* fifo;
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U16 width;
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U16 height;
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U16 bpp;
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U64 fb;
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U32 capabilities;
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};
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#define VMWGFX_FIFO_STATIC_SIZE (1024 * 1024)
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#define VMSVGA_MAGIC 0x900000
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#define VMSVGA_ID_2 (VMSVGA_MAGIC << 8 | 2)
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#define VMSVGA_MOUSE_ID 1
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#define VMSVGA_CAP_GMR 0x00100000
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#define VMSVGA_CMD_INVALID_CMD 0
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#define VMSVGA_CMD_UPDATE 1
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#define VMSVGA_CMD_RECT_COPY 3
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#define VMSVGA_CMD_DEFINE_CURSOR 19
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#define VMSVGA_CMD_DEFINE_ALPHA_CURSOR 22
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#define VMSVGA_CMD_UPDATE_VERBOSE 25
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#define VMSVGA_CMD_FRONT_ROP_FILL 29
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#define VMSVGA_CMD_FENCE 30
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#define VMSVGA_CMD_ESCAPE 33
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#define VMSVGA_CMD_DEFINE_SCREEN 34
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#define VMSVGA_CMD_DESTROY_SCREEN 35
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#define VMSVGA_CMD_DEFINE_GMRFB 36
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#define VMSVGA_CMD_BLIT_GMRFB_TO_SCREEN 37
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#define VMSVGA_CMD_BLIT_SCREEN_TO_GMRFB 38
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#define VMSVGA_CMD_ANNOTATION_FILL 39
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#define VMSVGA_CMD_ANNOTATION_COPY 40
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#define VMSVGA_CMD_DEFINE_GMR2 41
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#define VMSVGA_CMD_REMAP_GMR2 42
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#define VMSVGA_REG_ID 0
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#define VMSVGA_REG_ENABLE 1
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#define VMSVGA_REG_WIDTH 2
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#define VMSVGA_REG_HEIGHT 3
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#define VMSVGA_REG_MAX_WIDTH 4
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#define VMSVGA_REG_MAX_HEIGHT 5
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#define VMSVGA_REG_DEPTH 6
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#define VMSVGA_REG_BITS_PER_PIXEL 7 /* Current bpp in the guest */
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#define VMSVGA_REG_PSEUDOCOLOR 8
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#define VMSVGA_REG_RED_MASK 9
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#define VMSVGA_REG_GREEN_MASK 10
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#define VMSVGA_REG_BLUE_MASK 11
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#define VMSVGA_REG_BYTES_PER_LINE 12
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#define VMSVGA_REG_FB_START 13 /* (Deprecated) */
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#define VMSVGA_REG_FB_OFFSET 14
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#define VMSVGA_REG_VRAM_SIZE 15
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#define VMSVGA_REG_FB_SIZE 16
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/* ID 0 implementation only had the above registers then the palette */
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#define VMSVGA_REG_CAPABILITIES 17
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#define VMSVGA_REG_MEM_START 18 /* (Deprecated) */
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#define VMSVGA_REG_MEM_SIZE 19
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#define VMSVGA_REG_CONFIG_DONE 20 /* Set when memory area configured */
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#define VMSVGA_REG_SYNC 21 /* See "FIFO Synchronization Registers" */
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#define VMSVGA_REG_BUSY 22 /* See "FIFO Synchronization Registers" */
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#define VMSVGA_REG_GUEST_ID 23 /* Set guest OS identifier */
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#define VMSVGA_REG_CURSOR_ID 24 /* (Deprecated) */
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#define VMSVGA_REG_CURSOR_X 25 /* (Deprecated) */
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#define VMSVGA_REG_CURSOR_Y 26 /* (Deprecated) */
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#define VMSVGA_REG_CURSOR_ON 27 /* (Deprecated) */
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#define VMSVGA_REG_HOST_BITS_PER_PIXEL 28 /* (Deprecated) */
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#define VMSVGA_REG_SCRATCH_SIZE 29 /* Number of scratch registers */
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#define VMSVGA_REG_MEM_REGS 30 /* Number of FIFO registers */
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#define VMSVGA_REG_NUM_DISPLAYS 31 /* (Deprecated) */
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#define VMSVGA_REG_PITCHLOCK 32 /* Fixed pitch for all modes */
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#define VMSVGA_REG_IRQMASK 33 /* Interrupt mask */
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/* Legacy multi-monitor support */
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#define VMSVGA_REG_NUM_GUEST_DISPLAYS \
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34 /* Number of guest displays in X/Y direction */
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#define VMSVGA_REG_DISPLAY_ID \
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35 /* Display ID for the following display attributes */
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#define VMSVGA_REG_DISPLAY_IS_PRIMARY \
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36 /* Whether this is a primary display \
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*/
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#define VMSVGA_REG_DISPLAY_POSITION_X 37 /* The display position x */
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#define VMSVGA_REG_DISPLAY_POSITION_Y 38 /* The display position y */
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#define VMSVGA_REG_DISPLAY_WIDTH 39 /* The display's width */
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#define VMSVGA_REG_DISPLAY_HEIGHT 40 /* The display's height */
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/* See "Guest memory regions" below. */
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#define VMSVGA_REG_GMR_ID 41
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#define VMSVGA_REG_GMR_DESCRIPTOR 42
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#define VMSVGA_REG_GMR_MAX_IDS 43
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#define VMSVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH 44
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#define VMSVGA_REG_TRACES \
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45 /* Enable trace-based updates even when FIFO is on */
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#define VMSVGA_REG_GMRS_MAX_PAGES \
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46 /* Maximum number of 4KB pages for all GMRs */
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#define VMSVGA_REG_MEMORY_SIZE \
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47 /* Total dedicated device memory excluding FIFO */
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#define VMSVGA_REG_TOP 48 /* Must be 1 more than the last register */
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#define VMSVGA_FIFO_MIN 0
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#define VMSVGA_FIFO_MAX 1
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#define VMSVGA_FIFO_NEXT_CMD 2
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#define VMSVGA_FIFO_STOP 3
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#define VMSVGA_FIFO_CAPABILITIES 4
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#define VMSVGA_FIFO_FLAGS 5
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#define VMSVGA_FIFO_FENCE 6
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#define VMSVGA_FIFO_3D_HWVERSION 7
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#define VMSVGA_FIFO_PITCHLOCK 8
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#define VMSVGA_FIFO_CURSOR_ON 9
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#define VMSVGA_FIFO_CURSOR_X 10
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#define VMSVGA_FIFO_CURSOR_Y 11
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#define VMSVGA_FIFO_CURSOR_COUNT 12
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#define VMSVGA_FIFO_CURSOR_LAST_UPDATED 13
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#define VMSVGA_FIFO_RESERVED 14
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#define VMSVGA_FIFO_CURSOR_SCREEN_ID 15
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#define VMSVGA_FIFO_DEAD 16
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#define VMSVGA_FIFO_3D_HWVERSION_REVISED 17
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#define VMSVGA_FIFO_3D_CAPS 18
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#define VMSVGA_FIFO_3D_CAPS_LAST = 19
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#define VMSVGA_FIFO_GUEST_3D_HWVERSION 20
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#define VMSVGA_FIFO_FENCE_GOAL 21
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#define VMSVGA_FIFO_BUSY 22
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#define VMSVGA_FIFO_NUM_REGS 23
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#define VMSVGA_FIFO_CAP_NONE 0
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#define VMSVGA_FIFO_CAP_FENCE (1 << 0)
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#define VMSVGA_FIFO_CAP_ACCELFRONT (1 << 1)
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#define VMSVGA_FIFO_CAP_PITCHLOCK (1 << 2)
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#define VMSVGA_FIFO_CAP_VIDEO (1 << 3)
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#define VMSVGA_FIFO_CAP_CURSOR_BYPASS_3 (1 << 4)
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#define VMSVGA_FIFO_CAP_ESCAPE (1 << 5)
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#define VMSVGA_FIFO_CAP_RESERVE (1 << 6)
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#define VMSVGA_FIFO_CAP_SCREEN_OBJECT (1 << 7)
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#define VMSVGA_FIFO_CAP_GMR2 (1 << 8)
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// #define VMSVGA_FIFO_CAP_3D_HWVERSION_REVISED VMSVGA_FIFO_CAP_GMR2
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#define VMSVGA_FIFO_CAP_SCREEN_OBJECT_2 (1 << 9)
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#define VMSVGA_FIFO_CAP_DEAD (1 << 10)
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@vmsvga_info vmsvga;
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MemSet(&vmsvga, 0, sizeof(@vmsvga_info));
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U32 @vmsvga_reg_read(I64 index)
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{
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OutU32(vmsvga.io_base, index);
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return InU32(vmsvga.io_base + 1);
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}
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U0 @vmsvga_reg_write(I64 index, U32 val)
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{
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OutU32(vmsvga.io_base, index);
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OutU32(vmsvga.io_base + 1, val);
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}
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U0 @vmsvga_fifo_write(U32 value)
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{
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/* Need to sync? */
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if ((vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] + sizeof(U32) == vmsvga.fifo[VMSVGA_FIFO_STOP]) || (vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] == vmsvga.fifo[VMSVGA_FIFO_MAX] - sizeof(U32) && vmsvga.fifo[VMSVGA_FIFO_STOP] == vmsvga.fifo[VMSVGA_FIFO_MIN])) {
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//"Syncing because of full fifo\n";
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// vmwareWaitForFB(pVMWARE);
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}
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vmsvga.fifo[vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] / sizeof(U32)] = value;
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if (vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] == vmsvga.fifo[VMSVGA_FIFO_MAX] - sizeof(U32)) {
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vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] = vmsvga.fifo[VMSVGA_FIFO_MIN];
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} else {
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vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] += sizeof(U32);
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}
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}
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U0 @vmsvga_fifo_get_cap(U8* s, I64 cap)
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{
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"%32s:", s;
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if ((vmsvga.fifo[VMSVGA_FIFO_CAPABILITIES] & cap) == cap)
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"%s\n", "True";
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else
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"%s\n", "False";
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}
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I64 @vmsvga_init(I64 w, I64 h, I64 bpp)
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{
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I64 j;
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j = PCIClassFind(0x030000, 0);
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if (j < 0) {
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//"VMSVGA device not found.\n";
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return -1;
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}
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vmsvga.io_base = PCIReadU16(j.u8[2], j.u8[1], j.u8[0], 0x10) & ~(0x0F);
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@vmsvga_reg_write(VMSVGA_REG_ID, VMSVGA_ID_2);
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if (@vmsvga_reg_read(VMSVGA_REG_ID) == VMSVGA_ID_2) {
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//"VMSVGA driver version 2 supported.\n";
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} else {
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//"VMSVGA device not supported.\n";
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return -1;
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}
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vmsvga.width = w;
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vmsvga.height = h;
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vmsvga.bpp = bpp;
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vmsvga.fb = @vmsvga_reg_read(VMSVGA_REG_FB_START);
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vmsvga.fifo = @vmsvga_reg_read(VMSVGA_REG_MEM_START);
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//"FIFO @ 0x%08X (%d bytes)\n", vmsvga.fifo,
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// @vmsvga_reg_read(VMSVGA_REG_MEM_SIZE);
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@vmsvga_reg_write(VMSVGA_REG_WIDTH, 1920);
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@vmsvga_reg_write(VMSVGA_REG_HEIGHT, 1080);
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@vmsvga_reg_write(VMSVGA_REG_BITS_PER_PIXEL, 32);
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@vmsvga_reg_write(VMSVGA_REG_ENABLE, 1);
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vmsvga.fifo[VMSVGA_FIFO_MIN] = 16;
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vmsvga.fifo[VMSVGA_FIFO_MAX] = 16 + (10 * 1024);
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vmsvga.fifo[VMSVGA_FIFO_NEXT_CMD] = 16;
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vmsvga.fifo[VMSVGA_FIFO_STOP] = 16;
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@vmsvga_reg_write(VMSVGA_REG_CONFIG_DONE, 0);
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@vmsvga_fifo_write(VMSVGA_CMD_UPDATE);
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@vmsvga_fifo_write(0);
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@vmsvga_fifo_write(0);
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@vmsvga_fifo_write(0);
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@vmsvga_fifo_write(0);
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@vmsvga_reg_write(VMSVGA_REG_CONFIG_DONE, 1);
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return 0;
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}
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U0 @vmsvga_mouse_pointer_set(U32* pointer, I64 width, I64 height)
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{
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@vmsvga_reg_write(VMSVGA_REG_CONFIG_DONE, 0);
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@vmsvga_fifo_write(VMSVGA_CMD_DEFINE_ALPHA_CURSOR);
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@vmsvga_fifo_write(VMSVGA_MOUSE_ID);
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@vmsvga_fifo_write(0);
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@vmsvga_fifo_write(0);
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@vmsvga_fifo_write(width);
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@vmsvga_fifo_write(height);
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I64 x, y;
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for (y = 0; y < height; y++) {
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for (x = 0; x < width; x++) {
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@vmsvga_fifo_write(pointer[(y * width) + x]);
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}
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}
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@vmsvga_reg_write(VMSVGA_REG_CONFIG_DONE, 1);
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}
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U64 @vmsvga_get_framebuffer() { return vmsvga.fb; }
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U0 @vmsvga_display_update() { @vmsvga_reg_write(VMSVGA_REG_ENABLE, 1); }
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class @vmsvga
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{
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U0(*Init)
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(I64 w, I64 h, I64 bpp);
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U64(*FrameBuffer)
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();
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};
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@vmsvga VMSVGA;
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VMSVGA.FrameBuffer = &@vmsvga_get_framebuffer;
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VMSVGA.Init = &@vmsvga_init;
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"vmsvga ";
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